//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================

#ifndef __ELASTOS_PIC_H__
#define __ELASTOS_PIC_H__

// Registers' IO address
#define _INTSR1     ((ioport_t)0x80000240) // Interrupt Status Register 1
#define _INTMR1     ((ioport_t)0x80000280) // Interrupt Mask Register 1
#define _INTSR2     ((ioport_t)0x80001240) // Interrupt Status Register 2
#define _INTMR2     ((ioport_t)0x80001280) // Interrupt Mask Register 2
#define _INTSR3     ((ioport_t)0x80002240) // Interrupt Status Register 3
#define _INTMR3     ((ioport_t)0x80002280) // Interrupt Mask Register 3

#define _TC1EOI     ((ioport_t)0x800006C0) // TC1 End of Interrupt Location
#define _TC2EOI     ((ioport_t)0x80000700) // TC2 End of Interrupt Location

// INTMR1 Interrupt Mask Register 1
#define _TC1OI  __32BIT(8)  // TC1 under flow interrupt. This interrupt becomes
                            //  active on the next falling edge of the timer
                            //  counter 1 clock after the timer counter has
                            //  under flowed (reached zero). It is cleared by
                            //  writing to the TC1EOI location.
#define _TC2OI  __32BIT(9)  // TC2 under flow interrupt. This interrupt becomes
                            // active on the next falling edge of the timer
                            // counter 2 clock after the timer counter has
                            // under flowed (reached zero). It is cleared by
                            // writing to the TC2EOI location.


#endif // __ELASTOS_PIC_H__
